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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xr17c154 5v pci bus quad uart august 2005 rev. 1.3.2 general description the xr17c154 1 (154) is a quad pci bus universal asynchronous receiver and transmitter (uart) with same package and pin-out as the exar xr17x158 oc - tal uarts. the device is designed to meet today?s 32-bit pci bus and high bandwidth requirements in communication systems. the global interrupt source register provides a comple te interrupt status indica - tion for all 4 channels to speed up interrupt parsing. each uart is independently controlled and has its own 16c550 compatible 5g register set, transmit and receive fifos of 64 bytes, fully programmable trans - mit and receive fifo trigger levels, transmit and re - ceive fifo level counters, automatic hardware flow control with programmable hysteresis, automatic soft - ware (xon/xoff) flow control, irda (infrared data as - sociation) encoder/decoder, 8 multi-purpose defin - able inputs/outputs, and a 16-bit general purpose tim - er/counter. n ote : 1 covered by u.s. patents #5,649,122, #5,949,787 applications ? remote access servers ? ethernet network to serial ports ? network management ? factory automation and process control ? point-of-sale systems ? multi-port rs-232/rs-422/rs-485 cards features ? high performance quad uart ? pci bus 2.2 target interface compliance ? 5v pci bus compliant up to 33mhz clock ? 32-bit pci bus interface with eeprom interface ? a global interrupt source register for all 4 uarts ? data transfer in byte, word and double-word ? data read/write burst operation ? each uart is indepe ndently controlled with: ? 16c550 compatible 5g (fifth gen register set ? 64-byte transmit and receive fifos ? transmit and receive fifo level counters ? automatic rts/cts or dtr/dsr flow control ? automatic xon/xoff so ftware flow control ? automatic rs485 half-d uplex control output with 16 selectable turn-around delay ? infrared (irda 1.0) data encoder/decoder ? programmable data rate with prescaler ? up to 6.25 mbps serial data rate at 8x and 5v ? eight multi-purpose inputs/outputs ? a general purpose 16-bit timer/counter ? sleep mode with automatic wake-up indicator ? same package and pin-out as the xr17c158, xr17d154 and xr17d158 uart ? 20x20x1.4mm 144-lqfp package f igure 1. b lock d iagram tmrck device configuration registers xtal1 xtal2 crystal osc/buffer uart channel 0 tx0, rx0, dtr0#, dsr0#, rts0#, cts0#, cd0#, ri0# pci local bus interface clk (33mhz) rst# ad[31:0] c/be[3:0]# par frame# irdy# trdy# devsel# stop# idsel perr# serr# inta# configuration space registers . mpio0- mpio7 multi-purpose inputs/outputs tx3, rx3, dtr3#, dsr3#, rts3#, cts3#, cd3#, ri3# uart channel 3 uart channel 2 uart channel 1 16-bit timer/counter eeck eedi eedo eecs eeprom interface 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs 5v vcc gnd enir
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 2 f igure 2. p in o ut of the d evice ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr17c154cv 144-lead lqfp 0c to +70c active xr17c154iv 144-lead lqfp -40c to +85c active gnd mpio5 gnd tmrck enir xr17c154 144-lqfp 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 mpio0 mpio1 vcc gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ad24 cbe3 idsel vcc gnd ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 cbe2 frame# irdy# trdy# devsel# vcc stop# perr# serr# par cbe1 ad15 ad14 ad13 ad12 ad11 gnd vcc mpio7 mpio6 mpio4 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 eecs eedi eeck eedo vcc test# xtal1 xtal2 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 31 32 33 34 ad10 ad9 ad8 vcc 35 36 gnd cbe0 mpio2 78 77 76 75 74 73 mpio3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 vcc 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ad26 ad27 ad28 ad29 ad30 ad31 vcc gnd clk rst# 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 inta# ad25 nc nc nc nc nc nc nc nc rx0 cts0# dsr0# cd0# ri0# rts0# dtr0# tx0 rx1 cts1# tx1 dtr1# rts1# ri1# cd1# dsr1# nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc rx2 cts2# tx2 dtr2# rts2# ri2# cd2# dsr2# rx3 cts3# dsr3# cd3# ri3# rts3# dtr3# tx3 nc nc nc nc nc nc nc nc
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 3 pin descriptions pin description n ame p in # t ype d escription pci local bus interface rst# 134 i bus reset input (active low). it resets the pci local bus configuration space registers, device configuration regist ers and uart channel registers to the default condition, see table 19 . clk 135 i bus clock input of up to 33.34mhz at 5v. ad31-ad25, ad24, ad23-ad16, ad15-ad8, ad7-ad0 138-144, 1, 6-13, 26-33, 37-44 io address data lines [31:0] (bidirectional). frame# 15 i bus transaction cycle frame (active low). it indicates the beginning and dura - tion of an access. c/be3# - c/be0# 2, 14, 25, 36 i bus command/byte enable [3:0] (active low). this line is multiplexed for bus command during the address phase and byte enables during the data phase. irdy# 16 i initiator ready (active low). during a write, it indicates that valid data is present on data bus. during a read, it i ndicates the master is ready to accept data. trdy# 17 o target ready (active low). stop# 21 o target request to stop current transaction (active low). 5 idsel 3 i initialization device select (active high). devsel# 18 o device select to the xr17c154 (active low). inta# 133 od device interrupt from xr17c154 (open drain, active low). par 24 io parity is even across ad[31:0] and c/ be[3:0]# (bidirectional, active high). perr# 22 o parity error indicator to host (active low). optional in bus target application. serr# 23 od system error indicator to host (open drai n, active low). optional in bus target application. modem or serial i/o interface tx0 125 o uart channel 0 transmit data or infrared transmit data. normal txd output idles high while infrared txd output idles low. rx0 132 i uart channel 0 receive data or infrared receive data. normal rxd input idles high. the infrared pulses typically idle low but can be inverted inter - nally prior the decoder by fctr[4]. rts0# 127 o uart channel 0 request to send or general purpose output (active low). cts0# 131 i uart channel 0 clear to send or ge neral purpose input (active low). dtr0# 126 o uart channel 0 data terminal ready or general purpose output (active low). dsr0# 130 i uart channel 0 data set ready or general purpose input (active low). cd0# 129 i uart channel 0 carrier detect or general purpose input (active low). ri0# 128 i uart channel 0 ring indicator or general purpose input (active low). tx1 106 o uart channel 1 transmit data or infrared transmit data. normal txd output idles high while infrared txd output idles low. rx1 99 i uart channel 1 receive data or infrared receive data. normal rxd input idles high. the infrared pulses typically idle low but can be inverted inter - nally prior the decoder by fctr[4]. rts1# 104 o uart channel 1 request to send or general purpose output (active low).
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 4 cts1# 100 i uart channel 1 clear to send or ge neral purpose input (active low). dtr1# 105 o uart channel 1 data terminal ready or general purpose output (active low). dsr1# 101 i uart channel 1 data set ready or general purpose input (active low). cd1# 102 i uart channel 1 carrier detect or general purpose input (active low). ri1# 103 i uart channel 1 ring indicator or general purpose input (active low). tx2 88 o uart channel 2 transmit data or infr ared transmit data. normal txd output idles high while infrared txd output idles low. rx2 81 i uart channel 2 receive data or infrared receive data. normal rxd input idles high. the infrared pulses typically idle low but can be inverted inter - nally prior the decoder by fctr[4]. rts2# 86 o uart channel 2 request to send or general purpose output (active low). cts2# 82 i uart channel 2 clear to send or ge neral purpose input (active low). dtr2# 87 o uart channel 2 data terminal ready or general purpose output (active low). dsr2# 83 i uart channel 2 data set ready or general purpose input (active low). cd2# 84 i uart channel 2 carrier detect or general purpose input (active low). ri2# 85 i uart channel 2 ring indicator or general purpose input (active low). tx3 62 o uart channel 3 transmit data or infr ared transmit data. normal txd output idles high while infrared txd output idles low. rx3 55 i uart channel 3 receive data or infrared receive data. normal rxd input idles high. the infrared pulses typically idle low but can be inverted inter - nally prior the decoder by fctr[4]. rts3# 60 o uart channel 3 request to send or general purpose output (active low). cts3# 56 i uart channel 3 clear to send or ge neral purpose input (active low). dtr3# 61 o uart channel 3 data terminal ready or general purpose output (active low). dsr3# 57 i uart channel 3 data set ready or general purpose input (active low). cd3# 58 i uart channel 3 carrier detect or general purpose input (active low). ri3# 59 i uart channel 3 ring indicator or general purpose input (active low). ancillary signals mpio0 108 i/o multi-purpose input/output 0. the function of this pin is defined thru the con - figuration register mpiosel, mpio lvl, mpioinv, mpio3t and mpioint mpio1 107 i/o multi-purpose input/output 1. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio2 74 i/o multi-purpose input/output 2. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio3 73 i/o multi-purpose input/output 3. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio4 68 i/o multi-purpose input/output 4. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio5 67 i/o multi-purpose input/output 5. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio6 66 i/o multi-purpose input/output 6. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio7 65 i/o multi-purpose input/output 7. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. pin description n ame p in #t ype d escription
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 5 n ote : pin type: i=input, o=output, io= input/output, od=output open drain. eeck 116 o serial clock to eeprom. an internal clock of clk divide by 256 is used for reading the vendor and sub-vendor id du ring power up or reset. however, it can be manually clocked thru the configuration register regb. eecs 115 o chip select to a eeprom device like 93c46. it is manually selectable thru the configuration register regb. requires a pull-up 4.7k ohm resister for exter - nal sensing of eeprom during power up. see dan112 for further details. eedi 114 o write data to eeprom device. it is manually accessible th ru the configura - tion register regb. the 154 auto-configur ation register interface logic uses the 16-bit format. eedo 113 i read data from eeprom device. it is manually accessible thru the configu - ration register regb. xtal1 110 i crystal or external clock input of up to 50mhz for data rate of 3.125mbps at 5v. xtal2 109 o crystal or buffered clock output. tmrck 69 i 16-bit timer/counter ex ternal clock input. enir 70 i infrared mode enable (active high). this pin is sampled during power up, fol - lowing a hardware reset (rst#) or soft-re set (register reset). it can be used to start up all 4 uarts in the infrared mode. the sampled logic state is trans - ferred to mcr bit-6 in the uart. software can override this pin thereafter and enable or disable it. test# 111 i factory test. connect to vcc for normal operation. vcc 4,19,34,45,64, 90,112,137 pwr +5v (pci compliance). for 3. 3v operation, see the xr17d154. gnd 5,20,35,46,63, 89,136 pwr power supply common, ground. nc 47-54, 71,72,75-80, 91-98, 117-124 no connection. these pins are reserved and used by the octal pci uart xr17c158. pin description n ame p in #t ype d escription
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 6 functional description the xr17c154 (154) integrates the functions of 4 enhanced 16550 uart s with the pci local bus interface and a non-volatile memory interface for pci bus?s plug-a nd-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/ outputs, and an on-chip oscilla tor. the pci local bus is a synchronous timi ng bus where all bus transactions are associated to the bus clock of up to 33.34mhz. the 154 supports 32-bit wide read and write data transfer operations including data burst mode through the pci local bus interface. read and write data operations may be in byte, word or double-word (d word) format. a single 32-bit interrupt status register provides interrupts status for all 4 uarts, timer/counte r, multipurpose inputs/outputs, and a special sleep wake up indicator. there are three sets of register in the de vice. first, the pci local bus configuration registers for pci auto configuration. a set of device configuration re gisters for overall control, 32-bit wide transmit and re - ceive data transfer, and monitoring of the 4 uart c hannels. lastly, each uart channel has its own 16550 uart compatible configuration register set for individua l channel control, status, and byte wide data transfer. each uart has 64-byte fifos, automatic rts/cts or dtr/dsr hardware flow c ontrol with hysteresis con - trol, automatic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger level, fifo level counters, infrared encoder and decoder (irda ver. 1.0), programmable baud rate gen - erator with a prescaler of 1x or 4x, and data rate up to 6.25 mbps at 8x sampling clock. the xr17c154 bus timing and drive capability meets the pci local bus specif ication revision 2.2 for 5 vo lt operation over the tem - perature range. for a pin-to-pin compatible part that can operate at 3.3v, see the xr17d154. the xr17c154 is available in a thin 144-pin lqfp (20x20x1.4mm) pa ckage in commercial and industrial temperature ranges. pci l ocal b us i nterface this is the host interface and it meets the pci local bus specification revision 2.2. the pci local bus opera - tions are synchronous meaning each transaction is asso ciated to the bus clock. the xr17c154 can operate with the bus clock of up to a 33.34mhz. data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32- bit wide. with 32-bit data operations, it pushes the data transfer rate on the bus up to 132 mbyte/sec. this in - creases the overall system?s communication performance up to 16 times better than the 8-bit isa bus. see pci local bus specification revision 2.2 for bus operation details. pci local bus configuration space registers a set of pci local bus configuration space register is provided. these regist ers provide the pci local bus oper - ating system with the card?s vendor id, device id, s ub-vendor id, product model number, and resources and capabilities. the pci local bus operati ng system collects this data from all the cards on the bus during the auto configuration phase that follows immediately after a power up or system reset/reboot. after it has sorted out all devices on the bus, it defines and download the operating conditions to the cards. o ne of the definitions is the base address loaded into the base a ddress register (bar) where the card will be operating in the pci local bus memory space. eeprom interface an external 93c46 eeprom is only used to store the vendor?s id and model number, and the sub-vendor?s id and product model number. this information is only us ed with the plug-and-play auto configuration of the pci local bus. these data prov ide automatic hardware inst allation onto the pci bus. the eeprom interface con - sists of 4 signals, eedi, eedo, eecs, and eeck. the eep rom is not needed when aut o configuration is not required in the application. however, if your design requires non-volatile memory for other purpose. it is possi - ble to store and retrieve data on the eeprom through a special pci device configuration register. see applica - tion note dan112 for its programming details.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 7 1.0 xr17c154 registers the xr17c154 uart has three different sets of registers as shown in figure 3 . the pci local bus configura - tion space registers are for plug-and-play auto-configuration when connecting the device to the pci bus. this auto-configuration feature makes installation very easy in to a pci system and it is part of the pci local bus specification. the second register set is the device configuration registers that are accessible directly from the pci bus for programming general operat ing conditions of the device and mo nitoring the status of various func - tions. these registers are mapped into 2k of the pci bus memory address space. these functions include all 4 channel uart?s interrupt control and status, 16-bit general purpose timer control and status, multipurpose in - puts/outputs control and status, sleep mode, soft-reset, and device identifica tion and revision. and lastly, each uart channel has its own set of 5g internal uart co nfiguration registers for its own operation control and status reporting. all 4 sets of channel registers are em bedded inside the device configuration registers space, which provides faster access. the following paragraphs describe all 3 sets of registers in detail. 1.1 pci local bus configuration space registers the pci local bus configuration space registers are re sponsible for setting up the device?s operating environ - ment in the pci local bus. the pre-defined operating pa rameters of the device are read by the pci bus plug- and-play auto-configuration manager in the operating sys tem. after the pci bus has collected all data from ev - ery device/card on the bus, it defines and downloads the memory mapping inform ation to each device/card about their individual operation me mory address location and conditi ons. the operating memory mapped ad - dress location is downloaded into the base address re gister (bar) register, 0x10. the plug-and-play auto configuration feat ure is only available when an external 93c 46 eeprom is used. the eeprom contains the device vendor and sub-vendor data required by the auto-configuration setup. f igure 3. t he xr17c154 r egister s ets channel 0 int, mpio, timer, reg device configuration and uart[3:0] configuration registers are mapped on to the base address register (bar) in a 2k- byte of memory address space pci local bus target interface channel 0 channel 1 channel 2 channel 3 device configuration registers 4 channel interrupts, multipurpose i/os, 16-bit timer/counter, sleep, reset, dvid, drev uart[3:0] configuration registers 16550 compatib le and exar enhanced registers pci local bus configuration space registers for plug- and-play auto configuration pciregs-1 vendor and sub-vendor id and product model number in external eeprom 0x0000 0x0200 0x0400 0x0600 0x0080 0x07ff 0x0100
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 8 space, t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress b its t ype d escription r eset v alue ( hex ) 0x00 31:16 rwr 1 device id (exar device id number or from eeprom) 0x0154 15:0 rwr 1 vendor id (exar id or from eeprom) specified by pcisig 0x13a8 0x04 31:28 ro status bits (error reporting bits) 0000 27 r-reset target abort. set whenever 154 terminates with a target abort. 0 26:25 ro devsel# timing. 00 24 ro unimplemented bus master error reporting bit 0 23 ro fast back to back transactions are supported 1 22:16 ro reserved status bits 000 0000 15:9,7, 5,4,3,2 ro command bits (reserved) 0x0000 8 wo serr# driver enable. logic 1=enable driver and 0=disable driver 0 6 wo parity error enable. logic 1=respond to parity error and 0=ignore 0 1 rwr command controls a device?s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0 0 ro command controls a device?s response to i/o space accesses: 0 = disable i/o space accesses 1 = enable i/o space accesses 0 0x08 31:8 ro class code (simple 550 communication controller). 0x070002 7:0 ro revision id (exar devi ce revision number) current rev. value 0x0c 31:24 ro bist (built-in self test) 0x00 23:16 ro header type (a single function device with one bar) 0x00 15:8 ro unimplemented latency timer (needed only for bus master) 0x00 7:0 ro unimplemented cache line size 0x00 0x10 31:11 rw memory base address register (bar) 0x00 10:0 ro claims a 2k address space for the memory mapped uarts 0xx000 0x14 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x18h 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x1c 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x20 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x24 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x28 31:0 ro reserved 0x00000000
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 9 1.2 d evice configuration r egister s et the device configuration registers and a special way to access each of the uart?s transmit and receive data fifos are accessible directly from the pci data bus. this provides easy programming of general operating pa - rameters to the 154 uart and for monitoring the status of various functions. the registers occupy 2k of pci bus memory address space. these addresses are offset onto the basic memory address, a value loaded into the memory base address register ( bar) in the pci local bus configuratio n register set. these registers con - trol or report on all 4 channel uarts functions that include interrupt control and status, 16-bit general purpose timer control and status, mult ipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision, and others. the registers set is mapped into 4 address blocks where each uart channel occupies 512 bytes memory space for its own 16550 compatible configuration regist ers. the device configuratio n and control registers are embedded inside the uart channel zero?s address space between 0x0080 to 0x0093. all these registers can be accessed in 8, 16, 24 or 32 bit width depending on th e starting address given by the host at beginning of the bus cycle. transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register?s address. every time a read or write operation is made to the transmit or receive register, its fifo data pointer is automatically bumped to the next sequential data loca tion either in byte, word or dword. one special case applies to the receive data unloading when reading the re ceive data together with its lsr register content. the host must read them in 16 or 32 bits format in order to maintain integrity of the da ta byte with its associated error flags. 0x2c 31:16 rwr 1 subsystem id (write from external eeprom by customer) 0x0000 15:0 rwr 1 subsystem vendor id (write from external eeprom by cus - tomer) 0x0000 0x30 31:0 ro expansion rom base address (unimplemented) 0x00000000 0x34 31:0 ro reserved (returns zeros) 0x00000000 0x38 31:0 ro reserved (returns zeros) 0x00000000 0x3c 31:24 ro unimplemented maxlat 0x00 23:16 ro unimplemented mingnt 0x00 15:8 ro interrupt pin, use inta#. 0x01 7:0 rwr interrupt line. 0xxx rwr 1 =read/write from external eeprom. rwr=read/write from ad[31:0]. ro= re ad only. wo=write only. t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress b its t ype d escription r eset v alue ( hex )
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 10 t able 2: xr17c154 d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite d ata w idth c omment 0x000 - 0x00f uart channel 0 regs ( table 11 & table 12 ) 8/16/24/32 first 8 regs are 16550 compatible 0x010 - 0x07f reserved 0x080 - 0x093 device config. registers ( table 3 ) 8/16/24/32 0x094 - 0x0ff reserved 0x100 - 0x13f uart 0 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x100 - 0x13f uart 0 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x140 - 0x17f reserved 0x180 - 0x1ff uart 0 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x200 - 0x20f uart channel 1 regs ( table 11 & table 12 ) 8/16//24/32 first 8 regs are 16550 compatible 0x210 - 0x2ff reserved 0x300 - 0x33f uart 1 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x300 - 0x33f uart 1 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x340 - 0x37f reserved 0x380 - 0x3ff uart 1 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x400 - 0x40f uart channel 2 regs ( table 11 & table 12 ) 8/16/24/32 first 8 regs are 16550 compatible 0x410 - 0x4ff reserved 0x500 - 0x53f uart 2 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x500 - 0x53f uart 2 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x540 - 0x57f reserved 0x580 - 0x5ff uart 2 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x600 - 0x60f uart channel 3 regs ( table 11 & table 12 ) 8/16/24/32 first 8 regs are 16550 compatible 0x610 - 0x6ff reserved 0x700 - 0x73f uart 3 ? read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x700 - 0x73f uart 3 ? write fifo write-only 8/16/24/32 64 bytes of tx fifo data
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 11 0x740 - 0x77f reserved 0x780 - 0x7ff uart 3 ? read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr t able 2: xr17c154 d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite d ata w idth c omment
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 12 t able 3: d evice c onfiguration r egisters shown in byte alignment a ddress [a7:a0] r egister r ead /w rite c omment reset state ox080 int0 [7:0] read-only interrupt [3:0], reserved [7:4] bits 7-0 = 0x00 ox081 int1 [15:8] read-only bits 7-0 = 0x00 ox082 int2 [23:16] read-only [3:0], reserved [7:4] bits 7-0 = 0x00 ox083 int3 [31:24] reserved bits 7-0 = 0x00 ox084 timercntl read/write timer control bits 7-0 = 0x00 ox085 timer reserved bits 7-0 = 0x00 ox086 timerlsb read/write timer lsb bits 7-0 = 0x00 ox087 timermsb read/write timer msb bits 7-0 = 0x00 ox088 8xmode read/write bits 7-0 = 0x00 ox089 rega reserved bits 7-0 = 0x00 ox08a reset write-only self clear bits after executing reset [3:0] bits 7-0 = 0x00 ox08b sleep read/write sleep mode [3:0] bits 7-0 = 0x00 ox08c drev read-only device revision bits 7-0 = 0x04 ox08d dvid read-only device identification bits 7-0 = 0x24 ox08e regb write-only bits 7-0 = 0x00 ox08f mpioint read/write mpio interrupt mask bits 7-0 = 0x00 ox090 mpiolvl read/write mpio level control bits 7-0 = 0x00 ox091 mpio3t read/write mpio output control bits 7-0 = 0x00 ox092 mpioinv read/write mpio input polarity select bits 7-0 = 0x00 ox093 mpiosel read/write mpio select bits 7-0 = 0xff t able 4: d evice c onfiguration r egisters shown in dword alignment a ddress r egister b yte 3 [31:24] b yte 2 [23:16] b yte 1 [15:8] b yte 0 [7:0] 0x080 - 083 interrupt (read-only) int3 int2 int1 int0 0x084-087 timer (read/write) timermsb timerlsb timer (reserved) timercntl 0x088-08b ancillary1 (read/write) sleep reset rega (reserved) 8xmode 0x08c-08f ancillary2 (read-only) mpioint regb dvid drev 0x090-093 mpio (read/write) mpiosel mpioinv mpio3t mpiolvl
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 13 1.2.1 the interrupt status register the xr17c154 has a 32-bit wide register [int0, int1, int2 and int3] to provide interrupt information and supports two interrupt schemes. the first scheme uses bi ts 0 to 3 of an 8-bit indicator (int0) representing channels 0 to 3 of the xr17c154, respectively. this per mits the interrupt routine to quickly vector and serve that uart channel and determine the source(s) in each i ndividual routines. int0 bit-0 represents the interrupt status for uart channel 0 when its transmitter, receiver , line status, or modem port status requires service. other bits in the int0 register provide indication for the other channels with bit-3 representing uart channel 3 respectively. bits 4 through 7 are reserved and remain at a logic 0. the second scheme provides detail about the source of the interrupts for each uart channel. all the interrupts are encoded into a 3-bit code. this 3-bit code represen ts 7 interrupts corresponding to individual uart?s transmitter, receiver, line status, modem port status. int1 and int2 registers provide the 12-bit interrupt status for all 4 channels. bits 8, 9 and 10 representing cha nnel 0 and bits 17, 18 and 19 representing channel 3 respectively. bits 20 to 31 are reserved and remain at a logic 0. all 4 channel interrupts status are available with a single dword read operatio n. this feature allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host bandwidth requirement. figure 4 shows the 4-byte interrupt register and its make up. a special interrupt condition is generated by the 154 when it wakes up from sleep mo de. this special interrupt is cleared by reading the int0 register . if there are not any other interrupts pending, the value read from int0 would be 0x00. int0 [7:0] channel interrupt indicator each bit gives an indication of the channel that has requ ested for service. bit-0 repr esents channel 0 and bit-3 indicates channel 3. logic 1 indicates that a channel has called for service. bits 4 to 7 are reserved and remain at a logic 0. the interrupt bit clears after reading the appropriate register of the interrupting channel register, see interrupt clearing section. int3, int2 and int1 [32:8] twenty four bit encoded interrupt indicator. each channel?s interrupt is encoded into 3 bits for receive, transmit, and status. bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. the 3 bit encoding and their priority order are shown below in table 5 . the timer and mpio interrupts are for the device and therefore they exist within channel 0 space (bits [10:8]) and not in other channel. global interrupt register (dword) [default 0x00-00-00-00] int3 [31:24] int2 [23:16] int1 [15:8] int0 [7:0] the int0 register provides indi vidual status for each channel int0 register individual uart channel interrupt status rsvd ch-3 ch-2 ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 14 . f igure 4. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 t able 5: uart c hannel [3:0] i nterrupt s ource e ncoding p riority b it [ n +2] b it [ n +1] b it [ n ] i nterrupt s ource ( s ) x 0 0 0 none 1 0 0 1 rxrdy and rx line status (logic or of lsr[4:1]) 2 0 1 0 rxrdy time-out 3 0 1 1 txrdy, thr or tsr ( auto rs485 mode) empty 4 1 0 0 msr, rts/cts or dtr/dsr delta or xoff /xon det. or special char. detected 5 1 0 1 reserved. 6 1 1 0 mpio pin(s). available only within channel 0, reserved in other channels. 7 1 1 1 timer time-out. available only within channel 0, reserved in other chan - nels. t able 6: uart c hannel [3:0] i nterrupt c learing rxrdy is cleared by reading data in the rx fi fo until it falls below the trigger level. rxrdy time-out is cleared by readi ng data until the rx fifo is empty. rx line status interrupt clears after reading the lsr register. txrdy interrupt clears after reading isr register that is in the uart channel register set. modem status register interrupt clears after reading msr register that is in the uart channel register set. rts/cts or dtr/dsr delta interrupt clears after reading ms r register that is in the uart channel register set. xoff/xon interrupt clears after reading the isr regi ster that is in the uart channel register set. special character detect interrupt is cleared by a read to isr or after the next character is received. timer time-out interru pt clears after reading the timercntl register th at is in the device configuration register set. mpio interrupt clears after reading th e mpiolvl register that is in the device configuration register set. channel-3 channel-2 channel-1 channel-0 int2 register int1 register int3 register int0 register interrupt registers, int0, int1, int2 and int3 bit-0 bit-1 bit-2 bit-3 bit-7 bit-4 bit-5 bit-6 ch-3 ch-2 ch-1 ch-0 bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 15 1.2.2 general purpose 16-bit timer/counter [timermsb, ti melsb, timer, timecntl] ( default 0 x xx-xx-00-00) a 16-bit down-count timer for general purpose timer or counter. its clock source may be selected from internal crystal oscillator or externa lly on pin tmrck. the timer can be set to be a single-shot fo r a one-time event or re-triggerable for continue interval. an interrupt may be generated in the int register when the timer times out. it is controlled through 4 configuration register s [timercntl, timer, timelsb, timermsb]. these registers provide start/stop and re-triggerable or one-shot operation. the time-out output of the timer can be set to generate an interrupt for system or event alarm. timer [15:8] reserved f igure 5. t imer /c ounter circuit . t able 7: timer control r egisters timercntl [0] logic 0 (default) disables timer-counter interrupt and logic one enables the interrupt, reading the timercntl clears the interrupt. timercnlt [1] logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter. timercntl [2] logic 0 (default) selects re-trigger timer functi on and logic one selects one-shot (timer function. timercntl [3] logic 0 (default) selects internal and logic one selects external clock to the timer/counter. timercntl [4] routes the timer-counter interrupt to mpio[0 ] if mpiosel[0]=0 for external event control. timercntl [7:5] reserved (defaults to zero) tmrck osc. clock timercntl [3] 16-bit timer/counter timercntl [2] re-trigger single-shot timercntl [1] start/stop timercntl [0] timer interrupt, ch-0 int=7 time-out timer interrupt enable single/re-triggerable timermsb and timerlsb (16-bit value) 0 1 0 1 0 1 no interrupt clock select timercntl [4] 0 1 mpio[0] mpiolvl[0] timercntl register rsvd rsvd rsvd mpio[0] control clock select single/ re-trigger start/ stop int enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 16 timermsb [31:24] and timerlsb [23:16] timermsb and timerlsb form a 16-bit value. the least-significant bit of the timer is being bit [0] of the timerlsb with most-significant -bit being bit [7] in timermsb. notice that these registers do not hold the current counter value when read. reading the timercntl re gister will clear its interrupt. default value is zero (timer disabled) upon powerup and reset. 1.2.3 8xmode [7:0] (default 0x00) each bit selects 8x or 16x sampling rate for that uart channel, bit-0 is channel 0. logic 0 (default) selects normal 16x sampling with logic one se lects 8x sampling rate. transmit and receive data rates will double by selecting 8x. 1.2.4 rega [15:8] reserved 1.2.5 reset [23:16] (default 0x00) bits 0 to 3 of the reset re gister [reset] provides the software with t he ability to reset the uart(s) when there is a need. each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. all registers in that channel will be reset to the default condition, see table 19 for details. bit-0 =1 resets uart channel 0 with bit-3=1 resets channel 3 timermsb register bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 timerlsb register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 16-bit timer/counter programmable registers rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 8xmode register individual uart channel 8x clock mode enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 reset register individual uart channel reset enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 17 1.2.6 sleep [31:24 ](default 0x00) each uart can be separately enabled to enter sleep mode through the sleep register. sleep mode reduces power consumption when the system needs to put the uart(s) to idle. all of these conditions must be satisfied for the 154 to enter sleep mode: ? no interrupts pending (int0 = 0x00) ? divisor is a non-zero value for all channels (ie. dll = 0x1) ? sleep mode is enabled (sleep = 0x0f) ? modem inputs for all channels are not toggling (msr bits 0-3 = 0) ? rx input pins for all channels are idling high the 154 stops its crystal oscillator to conserve power in the sl eep mode. user can che ck the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 154 resumes normal operation by any of the following: ? a receive data start bit transition (high to low) ? a data byte is loaded to the transmitter, thr or fifo ? a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the 154 is awakened by any one of the above conditions , it will return to the sleep mode automatically after all interrupting conditions have been serviced and clea red. if the 154 is awakened by the modem inputs, a read to the msr is required to reset th e modem inputs. in any case, the sle ep mode will not be en tered while an in - terrupt is pending from any ch annel. the 154 will stay in th e sleep mode of o peration until it is disabled by set - ting sleep = 0x00. in this case, the quad uart is aw aken by any of the uart channel from a receive data byte or a change on the serial port. the uart is ready after 32 crystal clocks to ensure full functionality. also, a special interrupt is generated with an indication of no pendi ng interrupt. reading int0 will clear this special interrupt. logic 0 (default) is disable and logic 1 is enable to sleep mode. 1.2.7 device identification and revision there are two internal registers that provide device iden tification and revision, dvid and drev registers. the 8-bit content in the dvid register provides device ident ification. a return value of 0x24 from this register indicates the device is a xr17c154. the drev register re turns an 8-bit value of 0x01 for revision a with 0x02 equals to revision b and so forth. this information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. dvid [15:8] device identification for the type of uart. the upper nibb le indicates it is a xr17cxxx series with lower nibble indicating the number of channels. examples: xr17c158 or xr17d158 = 0x28 xr17c154 or xr17d154 = 0x24 xr17c152 or xr17d152 = 0x22 drev [7:0] revision number of the xr17c154. a 0x01 represen ts "revision-a" with 0x02 for rev-b and so forth. sleep register individual uart channel sleep enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd ch-3 ch-2 ch-1 ch-0 rsvd rsvd rsvd
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 18 regb [23:16] (default 0x00) regb register provides a control for simultaneous write to all 8 uarts configuration register or individually. this is very useful for device initia lization in the power up and reset rout ines. also, the register provides a facility to interface to th e non-volatile memory devic e such as a 93c46 eeprom. in embedded applications, the user can use th is facility to store proprietary data. 1.2.9 multi-purpose inputs and outputs the 154 provides 8 multi-purpose inputs/outputs [mpio7:0] for general use. each pin can be programmed to be an input or output function. the input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. the outputs can be set to be norma l high or low state, or 3- state. their functions and definitions are programmed through 5 registers: mpio int, mpiolvl, mpio3t, mpioinv and mpiosel. if all 8 pins are set for inputs, all 8 interrupts would be or?ed together. the or?ed interrupt is reported in the channel 0 uart interrupt status (3-bit interrupt encoding, bits [10: 8], in the global interrupt status register. the pins may also be programmed to be outputs and to the 3-state condition for signal sharing. 1.2.10 mpio register bit 7 represents mpio7 pin and bit 0 represents mpio0 pin. there are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. figure 6 shows the internal circuitry. 1.2.8 regb register regb[16](read/write) logic 0 (default) write to each uart configuration registers individually. logic 1 enables simultaneous write to all 8 uarts configuration register. regb[19:17] reserved regb[20] (write-only) control the eeck, clock, output (pin 116) on the eeprom interface. regb[21] (write-only) control the eecs, chips select, output (pin 115) to the eeprom device. regb[22] (write-only) eedi (pin 114) data input. writ e data to the eeprom device. regb[23] (read-only) eedo (pin 113) data output. read data from the eeprom device.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 19 mpioint [7:0] (default 0x00) enable multipurpose input pin interrupt. if the mpio pin is selected by mpiosel as input then bit-0 enables input pin 0 for interrupt, and bit-7 enables input pin 7. no interrupt is enable if the pin is selected to be an output. the interrupt is edge sensing and determined by mpioinv and mpiolvl registers. the mpio interrupt clears after a read to register mpiolvl. the combin ation of mpiolvl and mpioinv determines the interrupt being active low or active high, it?s level trigger. logic 0 (default) disables the pin?s interrupt and logic 1 enables it. f igure 6. m ultipurpose input / output internal circuit mpio pin [7:0] mpiolvl [7:0] read input level mpioint [7:0] rising edge detection int or and and 1 0 mpiosel [7:0] (select input=1, output=0 ) mpio3t [7:0] (3-state enable =1) mpiolvl [7:0] (output level) mpioinv [7:0] (input inversion enable =1) mpiockt mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioint register multipurpose input/output interrupt enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 20 mpiolvl [7:0] (default 0x00) output pin level control and input level status. the status of the input pin(s) is read on this register and output pins are controlled on this register. a logic 0 (default) se ts the output to low and a logic 1 sets the output pin to high. the mpio interrupt will clea r upon reading this register. mpio3t [7:0] (default 0x00) output pin tri-state control. a logic 0 (default) sets the output to active level per register mpio3t settling, a logic 1 sets the output pin to tri-state. mpioinv [7:0] (default 0x00) input inversion control. a logic 0 (default) does not inve rt the input pin logic. a logic 1 inverts the input logic level. mpiosel [7:0] (default 0xff) multipurpose input/output pin select. this register defines the functions of the pins. a logic 1 (default) defines the pin for input and a logic 0 for output. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiolvl register multipurpose output level control bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpio3t register multipurpose output 3-state enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioinv register multipurpose input signal inversion enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiosel registe r multipurpose input/output selection bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 21 2.0 crystal oscillator / buffer the 154 includes an on-chip oscillator (xtal1 and xtal2) . the crystal oscillator provides the system clock to the baud rate generators (brg) in each of the 4 uarts, the 16-bit general purpose timer/counter and inter - nal logics. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. see programmable baud rate generator in the uart section for programming details. the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with 10-22 pf capacitance load, 100ppm) connected exte rnally between the xtal1 and xtal2 pins (see figure 7 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal 4 baud rate generators for standard or custom rates. however, for external clock frequencies greater than 24mhz, a 2k pull-up may be necessary on the xtal2 output (see figure 8 ). typical oscillator co nnections are shown in figure 7 . for fur - ther reading on oscilla tor circuit please see applicatio n note dan108 on exar?s web site. f igure 7. t ypical oscillator connections f igure 8. e xternal c lock c onnection for e xtended d ata r ate c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k 2k xtal1 xtal2 r1 vcc external clock vcc gnd
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 22 3.0 transmit and receive data there are two methods to load transmit data and unload receive data from each uart channel. first, there is a transmit data register and receive data register for each uart channel in the dev ice configuration register set to ease programming. these registers support 8, 16 , 24 and 32 bits wide format. in the 32-bit format, it increases the data transfer rate on the pci bus. additionally, a special register location provides receive data byte with its associated error flags. this is a 16-bit or 32-bit read operation where the line status register (lsr) content in the uart channel regi ster is paired along with the data byte . this operation fu rther facilitates data unloading with the error flags without having to read the lsr register separately. furthermore, the xr17c154 supports pci burst mode for read/write operation of up to 64 bytes of data. the second method is through each uart channel?s transmit holding register (thr) and receive holding register (rhr). the thr and rhr registers are 16550 compatible so their access is limited to 8-bit format. the software driver must separately read the lsr cont ent for the associated error flags before reading the data byte. 3.1 data loading and unloading via 32-bit pci burst transfers the xr17c154 supports pci burst read and pci burst wr ite transactions anywhere in the mapped memory region (except reserved areas). in addi tion, to utilize this feature fully, the device provides a separate memory location (apart from the 16550 register set) where the rx and the tx fifo can be read from/written to, as shown in table 2 . the following is an extract from the table showing the burstable memory locations: channel 0: rx fifo : 0x100 - 0x13f (64 bytes) tx fifo : 0x100 - 0x13f (64 bytes) rx fifo + status : 0x180 - 0x1ff (64 bytes data + 64 bytes status) channel 1: rx fifo : 0x300 - 0x33f (64 bytes) tx fifo : 0x300 - 0x33f (64 bytes) rx fifo + status : 0x380 - 0x3ff (64 bytes data + 64 bytes status) channel 2: rx fifo : 0x500 - 0x53f (64 bytes) tx fifo : 0x500 - 0x53f (64 bytes) rx fifo + status : 0x580 - 0x5ff (64 bytes data + 64 bytes status) channel 3: rx fifo : 0x700 - 0x73f (64 bytes) tx fifo : 0x700 - 0x73f (64 bytes) rx fifo + status : 0x780 - 0x7ff (64 bytes data + 64 bytes status) 3.1.1 normal rx fifo data unloading at locations 0x100, 0x300, 0x500, 0x700 the rx fifo data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation (maximum 16 dword reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2), and 0x700 (channel 3). this operation is at least 16 ti mes faster than reading the data in 64 separate 8-bit memory reads of rhr register (0x000 for channel 0, 0x 200 for channel 1, 0x400 for channel 2, and 0x600 for channel 3).
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 23 3.1.2 special rx fifo data unloading at locations 0x180, 0x380, 0x580, and 0x780 the xr17c154 also provides the same rx fifo data al ong with the lsr status information of each byte side- by-side, at locations 0x180 (channel 0), 0x380 (chann el 1), 0x580 (channel 2), and 0x780 (channel 3). the entire rx data along with the status can be download ed in a single pci burst read operation of 32 dword reads. the status and data bytes must be read in 16 or 32 bits format to maintain data integrity. the following tables show this clearly. 3.1.3 tx fifo data loading at locations 0x100, 0x300, 0x500, 0x700 the tx fifo data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 dword writes) at memory locations 0x100 (channel 0), 0x 300 (channel 1), 0x500 (channel 2), and 0x700 (channel 3). r ead rx fifo, with n o e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 read n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. r ead rx fifo, with lsr e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+1 fifo data n+1 lsr n+1 fifo data n+0 lsr n+0 read n+2 to n+3 fifo data n+3 lsr n+3 fifo data n+2 lsr n+2 etc pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+3 receive data byte n+2 receive data byte n+1 receive data byte n+0 pci bus data bit-0 channel 0 to 3 receivedata in 32-bit alignment through the configuration register address 0x0100, 0x0300, 0x0500 and 0x0700 pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+1 line status register n+1 r eceive data byte n+0 line status register n+0 pci bus data bit-0 channel 0 to 1 receive data with line status register in a 32-bit alignment through the configuration register address 0x0180 and 0x0380
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 24 3.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8-bit format the thr and rhr register address for channel 0 to channel 3 is shown in table 8 below. the thr and rhr for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. transmit data byte is loaded to the thr when writing to that address and receive data is unloaded from the rhr register when reading that address. both thr and rhr registers are 16c550 compatible in 8-bit format, so each bus operation can only write or read in bytes. w rite tx fifo b yte 3 b yte 2 b yte 1 b yte 0 write n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 write n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. t able 8: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 transmit data byte n+3 transmit data byte n+2 transmit data byte n+1 transmit data byte n+0 pci bus data bit-0 channel 0 to 3 transmit data in 32-bit alignment through the configuration register address 0x0100, 0x0300, 0x0500 and 0x0700 thr and rhr address locations for ch0 to ch3 (16c550 compatible) ch0 0x000 write thr ch0 0x000 read rhr ch1 0x200 write thr ch1 0x200 read rhr ch2 0x400 write thr ch2 0x400 read rhr ch3 0x600 write thr ch3 0x600 read rhr 784thrrhr1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 25 4.0 uart there are 4 uarts [channel 3:0] in the 154. each has it s own 64-byte of transmit and receive fifo, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. eight additional registers per uart were added for the exar enhanced features. 4.1 programmable baud rate generator each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the outpu t of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x or 8x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaul ts to a random value upon power up. therefore, the brg must be programmed during initializ ation to the operating data rate. programming the ba ud rate generator regi sters dlm and dll provides t he capability for selecting the operating data rate. table 9 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x clock rate. at 8x sampling rate, these data rates would double. when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s). f igure 9. b aud r ate g enerator divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16), with 8xmode [7:0] is 0 divisor (decimal) = (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8xmode [7:0] is 1 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x or 8x sampling rate clock to transmitter and receiver to other channels baud rate generator logic
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 26 4.2 transmitter the transmitter section comprises of a 64 bytes of fifo , a byte-wide transmit holding register (thr) and an 8-bit transmit shift register (tsr). thr receives a data byte from the host (non-fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit-0. tsr shifts out every data bit with the 16x or 8x internal clock. a bit time is 16 or 8 clock periods. the transmitte r sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the st op bit(s). the status of the thr and tsr are reported in the line status register (lsr bit-5 and bit-6). 4.2.1 transmit holding regi ster (thr) - write-only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least- significant-bit (bit-0) bec omes first data bit to go out. the thr is also the input register to the transmit fifo of 64 bytes when fifo operation is enabled by fcr bit-0. a thr empty interrupt can be generated when it is enabled in ier bit-1. 4.2.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr become s completely empty. t able 9: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 27 4.2.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 64 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. furthermore, with the rs485 half-duplex direction contro l enabled (fctr bit-5=1) the source of the transmit empty interrupt changes to tsr empty instead of thr em pty. this is to ensure the rts# output is not changed until the last stop bit of the last character is shifted out. 4.2.4 auto rs485 operation the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit-5. while transmitting, the rts# or dtr# signal is high. the rts# or dtr# signal changes from high to low after a specified delay indicated in msr[7:4] following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiv er to receive the remote station?s response. the delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. this delay prevents undes irable line signal disturbance that causes signal degradation. it also changes the transmitter empt y interrupt to tsr empty instead of thr empty. f igure 10. t ransmitter o peration in non -fifo m ode f igure 11. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock (8xmode register) transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below programmed trigger level (txtrg) and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (64-byte) txfifo1 16x or 8x clock (8xmode register) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 28 4.3 receiver the receiver section contains an 8-bit receive shift r egister (rsr) and receive holding register (rhr). the rsr uses the 16x or 8x clock for timing. it verifies an d validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an inter nal receiver counter starts counting at the 16x or 8x clock rate . after 8 or 4 clocks the start bit period should be at the center of the start bit. at this time the start bit is samp led and if it is still a logic 0 it is va lidated. evaluating the start bit in this manner prevents the receiver from assembling a false char acter. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 1-4. upon unloading th e receive data byte from rhr, the receive fifo pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon rece iving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive fifo trig ger level. this ti me-out delay is 4 word lengths as defined by lcr[1:0] plus 12 bits time. the rhr interrupt is enabled by ier bit-0. 4.3.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bi t register that holds a receive data byte from the receive shift register (rsr). it provides the receive data interface to the host processor. the host reads the receive data byte on this register whenever a data byte is trans ferred from the rsr. rhr also part of the receive fifo of 64 bytes by 11-bit wide, 3 extra bits are for the error flags to be in lsr register. when the fifo is enabled by fcr bit-0, it acts as the first-out register of the fifo as new data ar e put over the first-in register. the receive fifo pointer is bumped after the rhr register is re ad. also, the error flags associated wi th the data byte are immediately updated onto the line status register (lsr) bits 1-4. 4.3.2 receiver operation in non-fifo mode f igure 12. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x clock (8xmode register) receive data characters data bit validation error flags in lsr bits 4:2
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 29 4.3.3 receiver operation with fifo 4.4 automatic hardware (rts/cts or dtr/dsr) flow control operation automatic hardware rts/cts or dtr/ds r flow control is used to prevent data overrun to the local receiver fifo and remote receiver fifo. the rts#/dtr# output pin is used to request the remote unit to suspend/ restart data transmission while the cts#/dsr# input pin is monitored to suspend/restart the local transmitter. the auto rts/cts or dtr/dsr flow control features are individually selected to fit specific application requirement and enabled through efr bit-6 and 7 and mcr bit-2 for either rts/cts or dtr/dsr control signals. auto rts flow control must be started by asserting the rts# output pin low (mcr bit-1 = 1). similarly, auto dtr flow control must be started by asserting the dtr# output pin low (mcr bit-0 = 1). figure 14 shows in detail how automatic hardwa re flow control works. f igure 13. r eceiver o peration in fifo and f low c ontrol m ode t able 10: a uto rts/cts or dtr/dsr f low c ontrol s election mcr b it -2 efr b it -7 efr b it -6 h ardware f low c ontrol s election 0 1 x auto cts flow control enabled 0 x 1 auto rts flow control enabled 1 1 x auto dsr flow control enabled 1 x 1 auto dtr flow control enabled x 0 0 no hardware flow control receive data shift register (rsr) rxfifo1 16x or 8x sampling clock (8xmode reg.) error flags (64-sets) error flags in lsr bits 4:2 64 bytes by 11- bit wide fifo receive data characters fifo trigger=48 example: - fifo trigger level set at 48 bytes - rts/dtr hyasteresis set at +/-8 chars. data fills to 56 data falls to 40 data bit validation receive data fifo (64-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts#/dtr# de-asserts when data fills above the trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts#/dtr# re-asserts when data falls below the trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 30 two interrupts associated with auto rts/cts and dtr/dsr flow control have been added to give indication when rts#/dtr# pin or cts#/dsr# pin are de-asserted during operation. these interrupts are enabled by: ? setting efr bit-4 =1 to enable the shaded register bits ? setting ier bit-7 will enable the cts# /dsr# interrupt when these pins ar e de-asserted. the selection of cts# or dsr# is selected via mcr bit-2. see table 10 above for complete details. ? setting ier bit-6 will enable the rts#/d tr# interrupt when these pins are de-asserted. th e selection of rts# or dtr# is selected via mcr bit-2. see table 10 above for complete details. automatic hardware flow control is selected by setting bi ts 6 (rts) and 7 (cts) of the efr register to logic 1. if cts# pin transitions from low to high indicating a fl ow control request, isr bit- 5 will be set to logic 1, (if enabled via ier bit 6-7), and the uart will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input returns low, indicating more data may be sent. f igure 14. a uto rts/dtr and cts/dsr f low c ontrol o peration the local uart (uarta) starts data transfer by asserting -rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into it s fifo. if interrupt service latency is l ong and data is not being unloaded, uarta monitors its receive data fill level to match the upper th reshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 31 4.5 infrared mode each uart in the 154 includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the input pin enir conveniently activates all 8 uart channels to start up in the infrared mode. the enir pin is sampled when the rst# i nput is de-asserted. this global control pin enables the mcr bit-6 function in every uart channel register. after power up or a reset, the software can overwrite mcr bit-6 if so desired. enir and mcr bit-6 also disable its receiver while the transm itter is sending data. this prevents the echoed data from going to the receiver. the global activation enir pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. when the infrared feature is enabled, the transmit data outputs, tx[3:0], would idle low. like wise, the rx [3:0] inputs assume an idling condition when it is low. the infrared encoder sends out a 3/16 of a bit wide pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrar ed led, hence reduces the power consumption. see figure 15 below. the infrared decoder receives the input pulse from the infrared sensing diode on rx pin. each time the decoder senses a light pulse, it returns a logic zero to the data bit stream. the rx input signal may be inverted prior delivered to the input of the decoder via internal register setting. this option supports active low instead of normal active high pulse from some infrared modules on the market. f igure 15. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 32 4.6 internal loopback each uart channel provides an inte rnal loopback capabilit y for system di agnostic. the in ternal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 16 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx, rts# and dtr# pins are held high (idle or de-asserted state), and the cts#, dsr# cd# and ri# inputs are ignored. 4.7 uart channel configuration re gisters and address decoding the 4 sets of uart configuration registers are decode d using address lines a8 to a11 as show below. ad - dress lines a0 to a3 select the 16 registers in each channel. the first 8 registers are 16550 compatible with exar enhanced feature registers lo cated on the upp er 8 addresses. f igure 16. i nternal l oop b ack a11 a10 a9 a8 uart c hannel s election 0 0 0 0 0 0 0 1 0 1 0 1 0 0 2 0 1 1 0 3 tx [3:0] rx [3:0] modem / general purpose control logic internal bus lines and control signals rts# [3:0] mcr bit-4=1 vcc vcc vcc transmit shift register receive shift register cts# [3:0] dtr# [3:0] dsr# [3:0] ri# [3:0] cd# [3:0] op1# op2# rts# cts# dtr# dsr# ri# cd#
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 33 . t able 11: uart channel configuration registers a ddress r egister r ead /w rite c omments a3 a2 a1 a0 16550 c ompatible r egisters 0 0 0 0 rhr - receive holding register read-only lcr[7] = 0 0 0 0 0 thr - transmit holding register write-only lcr[7] = 0 0 0 0 0 dll - div latch low read/write lcr[7] = 1 0 0 0 1 dlm - div latch high read/write lcr[7] = 1 0 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 0 1 0 isr - interrupt status register read-only 0 0 1 0 fcr - fifo control register write-only 0 0 1 1 lcr - line control register read/write 0 1 0 0 mcr - modem control register read/write 0 1 0 1 lsr - line status register read-only 0 1 1 0 msr - modem status register read-only 0 1 1 0 rs485 turn-around delay register write-only 0 1 1 1 spr - scratch pad register read/write e nhanced r egisters 1 0 0 0 fctr - feature control register read/write 1 0 0 1 efr - enhanced function register read/write 1 0 1 0 txcnt - transmit fifo level counter read-only 1 0 1 0 txtrg - transmit fifo trigger level write-only 1 0 1 1 rxcnt - receive fifo level counter read-only 1 0 1 1 rxtrg - receive fifo trigger level write-only 1 1 0 0 xoff-1 - xoff character 1 write-only 1 1 0 0 xchar read-only xon,xoff rcvd. flags 1 1 0 1 xoff-2 - xoff character 2 write-only 1 1 1 0 xon-1 - xon character 1 write-only 1 1 1 1 xon-2 - xon character 2 write-only
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 34 t able 12: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 0 0 0 0 rhr r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 thr w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 dll r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 dlm r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 ier r/w 0/ 0/ 0/ 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable cts/ dsr# int. enable rts/ dtr# int. enable xon/xoff/ sp. char. int. enable 0 0 1 0 isr r fifos enable fifos enable 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 delta - flow cntl xoff/special char 0 0 1 0 fcr w rx fifo trigger rx fifo trigger 0/ 0/ dma mode tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 0 1 1 lcr r/w divisor enable set tx break set parity even par - ity parity enable stop bits word length bit-1 word length bit-0 0 1 0 0 mcr r/w 0/ 0/ 0/ internal lopback enable (op2) 1 (op1) 1 rts# pin control dtr# pin control brg prescaler ir enable xonany rts/dtr flow sel 0 1 0 1 lsr r/w rx fifo e rror tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run rx data ready 0 1 1 0 msr r cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# msr w rs485 dly-3 rs485 dly-2 rs485 dly-1 rs485 dly-0 reserved reserved reserved reserved 0 1 1 1 spr r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 user data 1 0 0 0 fctr r/w trg table bit-1 trg table bit-0 auto rs485 enable invert ir rx input rts/dtr hyst bit-3 rts/dtr hyst bit-2 rts/dtr hyst bit-1 rts/dtr hyst bit-0 1 0 0 1 efr r/w auto cts/dsr enable auto rts/dtr enable special char select enable ier [7:5], isr [5:4], fcr[5:4], mcr[7:5,2] msr[7:4] software flow cntl bit-3 software flow cntl bit-2 software flow cntl bit-1 software flow cntl bit-0 1 0 1 0 txcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 0 txtrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rxcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rxtrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 35 n ote : mcr bits 2 and 3 (op1 and op2 outputs) are not avai lable in the xr17c154. they are present for 16c550 compatibility during internal loopback, see figure 16 . 4.8 registers 4.8.1 receive holding regi ster (rhr) - read-only see ?section 4.3, receiver? on page 28 for complete details. 4.8.2 transmit holding regi ster (thr) - write-only see ?section 4.2, transmitter? on page 26 for complete details. 4.8.3 baud rate generator divisors (dll and dlm) - read/write the baud rate generator (brg) is a 16-bit counter th at generates the data rate for the transmitter and receiver. the baud rate is programmed through regist ers dll and dlm which are only accessible when lcr bit-7 is set to logic 1. see ?section 4.1, programmable baud rate generator? on page 25 for more detail. 4.8.4 interrupt enable re gister (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these inte rrupts are reported in the interrupt status register (isr) register and also encoded in int (int0-int3) register in the device configuration registers. ier versus r eceive fifo i nterrupt m ode o peration when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the rhr interrupts (see isr bits 3 and 4) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. ier versus r eceive /t ransmit fifo p olled m ode o peration when fcr bit-0 equals a logic 1 for fifo enable, resett ing ier bits 0-3 enables the 158 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bits 2-4 provides the type of receive data errors encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. 1 1 0 0 xchar r 0 0 0 0 0 0 xon det. indicator xoff det. indicator self-clear after read 1 1 0 0 xoff1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 1 xoff2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 0 xon1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 1 xon2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 12: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 36 ier[0]: rhr interrupt enable the receive data ready in terrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. a receive data timeout interrupt will be issued in the fifo mode when the receive fifo has not reached th e programmed trigge r level and the rx input has been idle for 4 character + 12 bit times. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable when auto rs485 mode operation is disabled (fctr bit- 5 = 0), this interrupt is associated with bit-5 in the lsr register. an interrupt is issued whenever the thr becomes empty or when data in the fifo falls below the programmed trigger level. when auto rs485 mode operation is enabled (fctr bit-5 = 1), this interrupt is associated with bit-6 in the lsr register. an interrupt is issued whenever the tx fifo and the tsr becomes empty. ? logic 0 = disable transmit holding re gister empty interrupt (default). ? logic 1 = enable transmit holding register empty interrupt. ier[2]: receive line status interrupt enable any of lsr register bits 1, 2, 3 or 4 will generate an lsr in terrupt immediately when a character received by the rx fifo has an error. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: reserved ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xo ff interrupt. see software flow control section for details. ier[6]: rts#/dtr# output interrupt enable (requires efr bit-4=1) the rts# or dtr# output is selected via mcr bit-2. see table 10 or mcr[2] for complete details. ? logic 0 = disable the rts#/dtr# interrupt (default). ? logic 1 = enable the rts#/dtr# interrupt. the uart issues an interrupt when the rts#/dtr# pin makes a transition. ier[7]: cts# input interrupt enable (requires efr bit-4=1) the cts# or dsr# input is selected via mcr bit-2. see table 10 or mcr[2] for complete details. ? logic 0 = disable the cts#/dsr# interrupt (default). ? logic 1 = enable the cts#/dsr# interrupt. the uart issues an interrupt when cts# pin makes a transi - tion. 4.8.5 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize exte rnal software interaction. the inter - rupt status register (isr) provides the user with six in terrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced with others queued up for next ser - vice. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 13 , shows the data values (bit 0-5) for the six priori tized interrupt levels and the interrupt sources associ - ated with each of th ese interrupt levels.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 37 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by the a 4-char plus 12 bits delay ti mer if the rx fifo level is less than the rx trigger level. ? txrdy is by lsr bit-5 (or bit-6 in auto rs485 control). ? msr is by any of the msr bits, 0, 1, 2 and 3. ? receive xon / xoff/special character is by detection of a xon, xoff or special character. ? cts#/dsr# is by a change of state on the input pin (from low to high) with auto flow control enabled, efr bit-7, and depending on selection of mcr bit-2. ? rts#/dtr# is when its receiver changes the state of the output pin (from low to high) during auto rts/ dtr flow control enabled by efr bi t-6 and selection of mcr bit-2. ? wake-up indicator: when the uart comes out of sleep mode. interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy is cleared by reading data until fifo falls below the trigger level. ? rxrdy time-out is cleared by readin g data until the rx fifo is empty. ? txrdy interrupt is cleared by a read to the isr register. ? msr interrupt is cleared by a read to the msr register. ? xon or xoff character interrupt is cleared by a read to isr register. ? special character interrupt is cleared by a read to isr register or after the next character is received. ? rts#/dtr# and cts#/dsr# status change interrupts are cleared by a read to the msr register. ? wake-up indicator is cleared by a read to the int0 register. ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (see interrupt source table 13 ). t able 13: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of the interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 0 1 0 0 rxrdy (received data ready) 3 0 0 1 1 0 0 rxrdy (receive data time-out) 4 0 0 0 0 1 0 txrdy (transmitter holding register empty) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xon/xoff or special character) 7 1 0 0 0 0 0 cts#/dsr#, rts#/dtr# change of state x 0 0 0 0 0 1 none (default)
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 38 isr[4]: xoff/xon or special character interrupt status this bit is enabled when efr bit-4 is set to a logic 1. is r bit-4 indicates that the receiver detected a data match of the xoff character(s). if this is an xoff/xon interrupt, it can be cleared by a read to the isr. reading the xchar register will indicate which character (xoff or xon) was received last. if it is a special character interrupt, it can be clear ed by reading isr or it will automatically cl ear after the next char acter is received. isr[5]: rts#/cts# interrupt status this bit is enabled when efr bit-4 is set to a logic 1. isr bit-5 indicates that the cts# or rts# has changed state from low to high. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.8.6 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode (legacy term that refers to "block transfer mode"). the dma and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is active. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is active. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo leve l counter logic (the transm it shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select this bit has no effect since txrdy and rxrdy pins are no t available in this device. it is provided for legacy software. dma is a legacy term used for block transfer mode. dma does not stand for "direct memory ac - cess." ? logic 0 = set dma to mode 0 (default). ? logic 1 = set dma to mode 1. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = 1) the fctr bits 6-7 are associated with these 2 bits by selecting one of the four tables. the 4 user selectable trigger levels in 4 tables are sup ported for compatibility reasons. these 2 bits set the trigger level for the transmit fifo interrup t. the uart will issue a transmit interrupt when the number of char acters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 14 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed. note that the receiver and the tr ansmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 39 fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 6-7 are associated with these 2 bits. thes e 2 bits are used to set the trigger level for the receiv - er fifo interrupt. table 14 shows the complete selections. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. t able 14: t ransmit and r eceive fifo t rigger l evel s election t rigger t able fctr b it -7 fctr b it -6 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility table a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580 compati - ble. table b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a compati - ble. table c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 compati - ble. table d 1 1 x x x x programmable programmable 16c850, 16c2850, 16c2852, 16c854, 16c864, 16l2750, 16l2751, 16l2752 compatible.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 40 4.8.7 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 15 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gene rated by forcing an even th e number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 41 lcr[6]: transmit break enable when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a ?space", low state). this condition remains unt il disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.8.8 modem control regi ster (mcr) - read/write the mcr register is used for cont rolling the modem interface signals or general purpose inputs/outputs. mcr[0]: dtr# pins the dtr# pin may be used for automatic hardware flow control enabled by efr bit-6 and mcr bit-2=1. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# pins the rts# pin may be used for automatic hardware flow control by enabled by efr bit-6 and mcr bit-2=0. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force rts# output high (default). ? logic 1 = force rts# output low. mcr[2]: dtr# or rts# for auto flow control dtr# or rts# auto hardware flow control select. this bi t is in effect only when auto rts/dtr is enabled by efr bit-6. dtr# selectio n is associated with dsr# and rts# is with cts#. ? logic 0 = uses rts# and cts# pins for auto hardware flow control. ? logic 1 = uses dtr# and dsr# pins for auto hardware flow control. mcr[3]: (op2) the op2 output is no t available in the xr17c154. it is presen t for 16c550 compatibilit y during internal loopback. see figure 16 . logic 0 is default. mcr[4]: internal loopback enable ? logic 0 = disable internal loopback mode (default). ? logic 1 = enable internal loopback mode, see loopback section and figure 16 . t able 15: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 42 mcr[5]: xon-any enable ? logic 0 = disable xon-any function (f or 16c550 compatib ility) (default). ? logic 1 = enable xon-any function. in this mode any rx character re ceived will enable xon, resume data transmission. mcr[6]: infrared encoder/decoder enable the state of this bit depends on the sampled logic level of pin enir during power up, following a hardware reset or a soft-reset. afterward user can override this bit for desired operation. ? logic 0 = disable the infrared mode, operates in the normal serial character mode. ? logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ input are routed to the in frared encoder /decoder. the data input and output levels will confor m to the irda infrared interface requir ement. as such, while in this mode the in frared tx output will be a logic 0 during idle data conditions. fctr bit-4 may be selected to invert the rx input signal level going to the decoder for infrared modules that provide rather an inverted output. mcr[7]: clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one-fourth. 4.8.9 line status register (lsr) - read/only this register provides the status of data transfers between the uart and the host. if ier bit-2 is set to a logic 1, an lsr interrupt will be generated immediately when any character in the rx fifo has an error (parity, framing, overrun, break). r eading lsr will clear lsr bits 4-1. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. this bit is cleared after lsr is read. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the charac ter available for reading in rhr. this bit is cleared after lsr is read. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. this bit is cleared after lsr is read. lsr[4]: receive break tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. this bit is cleared after lsr is read.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 43 lsr[5]: transmit holding register empty flag this bit is the transmit holding regi ster empty indicator. th is bit indicates that the transmitter is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the host when the thr inte rrupt enable is set. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift regist er. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in th e fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr[6]: transmit shift register empty flag this bit is the transmit shift register empty indicator. th is bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = an indicator for the sum of all error bits in th e rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit cl ears when there is no more error(s) in the fifo. 4.8.10 modem status register (msr) - read-only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interr upt is enabled (ier bit-3. msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7) and rts/cts flow control select (m cr bit-2). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the cu rrent character has fini shed transmission, and a logic 0 will resume data transmission. if automatic hardware flow control is not us ed, msr bit-4 bit is the comp liment of the cts# input. however in the loopback mode , this bit is equivalent to the rts# bi t in the mcr register . the cts# input may be used as a general purpose input when the modem interface is not used.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 44 msr[5]: dsr input status this input may be used for auto dtr/dsr flow control function, see ?section 4.4, automatic hardware (rts/cts or dtr/dsr) flow control operation? on page 29 for complete details. if automatic hardware flow control is not used, this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the ds r# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status this bit is the compliment of the ri# input. in the loopba ck mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general pu rpose input when the modem interface is not used. msr[7]: cd input status this bit is the compliment of the cd# input. in the lo opback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input 4.8.11 modem status register (msr) - write-only the upper four bits 4-7 of this register sets the delay in number of bits time for the auto rs485 turn around from transmit to receive. msr [7:4] when auto rs485 feature is enabled (fctr bit-5=1) and rts# output is connected to the enable input of a rs-485 transceiver. these 4 bits select from 0 to 15 bit-ti me delay after the end of the last stop-bit of the last transmitted character. this delay controls when to change th e state of rts# output. this delay is very useful in long-cable networks. table 16 shows the selection. the bits are enabled by efr bit-4. t able 16: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive msr[7] msr[6] msr[5] msr[4] d elay in d ata b it ( s ) t ime 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 9 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 45 4.8.12 scratch pad regist er (spr) - read/write this is an 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.8.13 feature control regi ster (fctr) - read/write fctr [3:0] - auto rts/dtr fl ow control hysteresis select these bits select the auto rts/dtr flow control hyster esis and only valid when tx and rx trigger table-d is selected (fctr bit-6 and 7 are set to logic 1). the rts/dtr hysteresis is referenced to the rx fifo trigger level. after reset, these bits are set to logic 0 selectin g the next fifo trigger level for hardware flow control. table 17 shows the 16 selectab le hysteres is levels. fctr[4]: infrared rx input logic select ? logic 0 = select rx input as active hi gh encoded irda data, normal, (default). ? logic 1 = select rx input as active low encoded irda data, inverted. fctr[5]: auto rs485 enable auto rs485 half duplex control enable/disable. ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register (thr) becomes empty. transmit shift regist er (tsr) may still be shifting data bit out. ? logic 1 = enable auto rs485 half duplex direction control. rts# output changes its logic level from high to low when finished sending the last stop bit of the last character out of the tsr register. it changes back to high from low when a data byte is loaded into the th r or transmit fifo. the change to high occurs prior sending the start-bit. it also changes the transmitter inte rrupt from transmit holding to transmit shift register (tsr) empty. fctr[7:6]: tx and rx fifo trigger table select these 2 bits select the transmit and receive fifo trigger level table a, b, c or d. when table a, b, or c is selected the auto rts flow c ontrol trigger level is set to "next fifo trigger level" for compatibility to st16c550 and st16c650 series. rts#/dtr# triggers on the next leve l of the rx fifo trigger level, in another word, one fifo level above and one fifo level below. see table 14 for complete selection with fcr bit 4-5 and fctr bit 6-7, i.e. if table c is used on th e receiver with rx fifo tr igger level set to 56 by tes, rts/dtr# output will de-assert at 60 and re-assert at 16.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 46 4.8.14 enhanced feature register (efr) - read/write enhanced features are enabled or disabled using this register. bits 0-3 provide single or dual consecutive character software flow control selection (see table 18 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concaten ated into two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select combinations of software flow control can be selected by programming these bits. see table 18 for complete selections. the xoff1/xoff2 characters are transmitte d approximately 2 character times after the rx fifo level has reached the rx trigger level, irrespective of which trigger table is used (trigger tables a-d). the xon1/xon2 characters are transmitted when the rx fifo level falls below the next lower trigger level for trigger tables a-c and they are transmitted when th e rx fifo level falls below the (rx trigger level - hysteresis level) for trigger table d. for example, if trigger table d is used with an rx trigger level of 56 and a hysteresis level of 16, the xon1/xon2 characters ar e sent when the rx fifo level count falls below 40. t able 17: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it -3 fctr b it -2 fctr b it -1 fctr b it -0 rts/dtr h ysteresis ( characters ) 0 0 0 0 0 0 0 0 1 4 0 0 1 0 6 0 0 1 1 8 0 1 0 0 8 0 1 0 1 16 0 1 1 0 24 0 1 1 1 32 1 1 0 0 12 1 1 0 1 20 1 1 1 0 28 1 1 1 1 36 1 0 0 0 40 1 0 0 1 44 1 0 1 0 48 1 0 1 1 52
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 47 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables the functi ons in ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch en hanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with the industry standard 16550 (default). ? logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features are enabled. efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incomi ng receive character with data in xoff-2 register. if a match ex ists, the received data will be transferr ed to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit for the receive character. if flow control is set for comparing xon1, xoff1 (efr [1:0]=?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]=?01?) then flow control works normally, but xoff2 will not go to the fifo, and will ge nerate an xoff interrupt and a special character interrupt. t able 18: s oftware f low c ontrol f unctions tx s/w flow contro l rx s/w flow control efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 s oftware f low c ontrol f unctions 0 0 x x no transmit flow control 0 1 x x transmit xon2, xoff2 1 0 x x transmit xon1, xoff1 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 0 1 receiver compares xon2, xoff2 x x 1 0 receiver compares xon1, xoff1 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 0 1 1 no transmit flow control receiver compares xon1 and xon2, xoff1 and xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2 receiver compares xon1 and xon2, xoff1 and xoff2
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 48 efr[6]: auto rts or dtr flow control enable rts#/dtr# output may be used for hardware flow contro l by setting efr bit-6 to logic 1. when auto rts/ dtr is selected, an in terrupt will be gener ated when the receive fifo is f illed to the progra mmed trigger level and rts#/dtr# will de-assert high at the next upper trigger or select ed hysteresis level. rts#/dtr# will return low when fifo data falls below the next lower trigger or selected hysteresis level (see fctr bits 4-7). the rts# or dtr# output must be asserted (low) befo re the auto rts/dtr can take effect. the selection for rts# or dtr# is through mcr bit-2. rts/dtr# pin will function as a g eneral purpose output when hardware flow control is disabled. ? logic 0 = automatic rts/dtr flow control is disabled (default). ? logic 1 = enable automatic rts/dtr flow control. efr[7]: auto cts flow control enable automatic cts or dsr flow control. ? logic 0 = automatic cts/dsr flow control is disabled (default). ? logic 1 = enable automatic cts/dsr flow control. transmission stop s when cts#/dsr# pin de-asserts high. transmission resumes when cts/ dsr# pin returns low. the selectio n for cts# or dsr# is through mcr bit-2. 4.8.15 txcnt[7:0]: transmit fi fo level counter - read-only transmit fifo level byte count from 0x00 (zero) to 0x40 (64). this 8-bit register gives an indication of the number of characters in the transmit fifo. the fifo le vel byte count register is read only. the user can take advantage of the fifo level byte counter for faster data loading to the transmit fifo, which reduces cpu bandwidth requirements. please see the application note dan119 on exar?s website for a detailed discussion of fifo level counters. due to the dynamic nature of the fifo counters, this register should be read until the same value is returned twice. 4.8.16 txtrg [7:0]: transmit fi fo trigger level - write-only an 8-bit value written to this register sets the tx fifo trigger level from 0x00 (zero) to 0x40 (64). the tx fifo trigger level generates an interrupt whenever the data leve l in the transmit fifo falls below this preset trigger level. 4.8.17 rxcnt[7:0]: receive fifo level counter - read-only receive fifo level byte count from 0x00 (zero) to 0x40 (64). it gives an indication of the number of characters in the receive fifo. the fifo level byte count register is read only. the user can take advantage of the fifo level byte counter for faster data unloading from the receiver fifo, which reduces cpu bandwidth requirements. please see the application note dan119 on exar?s website for a detailed discussion of fifo level counters. due to the dynamic natu re of the fifo counters, this regi ster should be read until the same value is returned twice. 4.8.18 rxtrg[7:0]: receive fifo trigger level - write-only an 8-bit value written to this register, sets the rx fifo trigger level from 0x00 (zero) to 0x40 (64). the rx fifo trigger level generates an interrupt whenever the receive fifo level rises to this preset trigger level.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 49 t able 19: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs spr bits 7-0 = 0xff fctr bits 7-0 = 0x00 efr bits 7-0 = 0x00 txcnt bits 7-0 = 0x00 txtrg bits 7-0 = 0x00 rxcnt bits 7-0 = 0x00 rxtrg bits 7-0 = 0x00 xchar bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx[ch-3:0] high (if enir pin = low) low (if enir pin = high) rts#[ch-3:0] high dtr#[ch-3:0] high eeck low eecs low eedi low
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 50 5.0 programming examples 5.1 u nloading r eceive d ata u sing the s pecial r eceive fifo d ata with s tatus it is suggested that before starting to read the special receive fifo data with status to unload data from any uart channel (address 0x180 for channel 0), do a dummy read to the device id (dvid) register in the config - uration register of the device. the special receive fifo data with status register can then be read multiple times subsequently without any byte-sw apping problem as long as no other re gister (except the device id reg - ister) is accessed in between data unload. if you must re ad or write to another register, make that dummy read to the dvid register again and continue with data unloading. a step by step procedure describing the sequence for a target channel is shown below. from the receive data service routine: ? do a dummy read to device id (dvid) register. address 0x8d in byte alignment or address 0x8c in dword alignment. ? read the data byte and its associated er ror status from ?special receive fifo da ta with status? register of the target channel until done or empty when one of the lsr status byte bit-0=0. note: if you must do other read/write operations to other register(s) during data unloading, repeat steps 1 & 2 to continue unloading data plus status from the ?special receive fifo data with status? register of the target channel. some examples of using the specia l receive fifo data with status: e xample i: p olling ..................... read lsr read dvid read special receive fifo data with st atus (address 0x180 for channel 0, etc) read special receive fifo data with stat us (address 0x180 for channel 0, etc)* read special receive fifo data with st atus (address 0x180 for channel 0, etc) .................... e xample 2: i nterrupt s ervice using i nterrupt i nformation in d evice c onfiguration r egister s et ..................... read global interrupt register int0 (address 0x080) read int1 through int3 registers to identify interrupting channel (address 0x081 through 0x083) read dvid read special receive fifo data with st atus (address 0x180 for channel 0, etc) read special receive fifo data with stat us (address 0x180 for channel 0, etc)* read special receive fifo data with st atus (address 0x180 for channel 0, etc) ................ e xample 3: i nterrupt s ervice using i nterrupt i nformation in i ndividual c hannel ? s r egisters ................ read global interrupt register int0 (address 0x080) read isr register of interrupting channel read dvid read special receive fifo data with st atus (address 0x180 for channel 0, etc) read special receive fifo data with stat us (address 0x180 for channel 0, etc)* read special receive fifo data with st atus (address 0x180 for channel 0, etc) ................ * in case some other registers need to be accessed in between ?special receive fifo data with status? reads, a ?read dvid? instruction has to be inserted before resuming ?special receive fifo data with status? read operation.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 51 absolute maximum ratings power supply range 7 volts voltage at any pin -0.5 to 7v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (20x20x1.4mm 144-lqfp) theta-ja = 42, theta-jc = 8 electrical characteristics dc electrical characteristics for 5v signaling ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package). vcc = 4.5 - 5.5v. s ymbol p arameter m in m ax u nits c ondition n otes v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 6.0 v v ol output low voltage 0.55 v iout=6 ma v oh output high voltage 2.4 v iout=-2 ma i il input low leakage cur - rent -10 ua i ih input high leakage cur - rent 10 ua i cl input clock leakage 10 ua c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf i cc power supply current 3 ma pci bus clk and ext. clock = 2mhz, all inputs at vcc or gnd and all outputs are unloaded. i sleep sleep current 20 ua all four uarts asleep. ad[31:0] at gnd, all inputs at vcc or gnd.
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 52 ac electrical characteristics for 5v signaling ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package). vcc = 4.5 - 5.5v. s ymbol p arameter m in m ax u nits n otes xtal1 uart crystal oscillator 24 mhz eclk external clock 50 mhz i oh(ac) switching current high -44 ma 0 xr xr17c154 rev. 1.3.2 5v pci bus quad uart 53 n ote : f igure 17. pci b us c onfiguration s pace r egisters r ead and w rite operation clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-rd byte enable# pcicfg_rd host host host host host target target target data transfer address data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-wr byte enable# pcicfg_wr host host host host host target target target data transfer address write data
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 54 f igure 18. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = byte byte transfer pci_rd1 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par data parity active host host host host host target host target target target data byte wait wait wait address parity serr# target targe t active data word byte enable# = dword dword transfer wait wait data parity active 91011
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 55 f igure 19. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o pera - tion clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = dword pci bwr 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target address parity serr# target target active data parity active 910 data dword data dword dword transfer dword transfer dword transfer dword transfer dword transfer data parity data parity data parity data parity active active active active 11 data dword data dword data dword
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 56 f igure 20. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 13 ad bus cmd byte enable# = dword pci_brd par perr# 18 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target serr# target target dword transfer dword transfer dword transfer dword transfer 23 8 ad data data data data active active active active active data data data
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 57 f igure 21. 5v pci b us c lock (dc to 33mh z ) 2.0 v p-t-p (minimum) 2.4 v 0.4 v clk bused signal output delay tri-state output tvalid (2-11 nsec) ton (2 nsec min) toff (28 nsec max) 11 nsec (min) 4 nsec (max) 4 nsec (max) 11 nsec (min) tsetup (7 nsec min) thold (0 nsec) bused signal input pci_clk inputs valid
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 58 f igure 22. t ransmit d ata i nterrupt at t rigger l evel f igure 23. r eceive d ata r eady i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx data next data start bit tx interrupt at transmit trigger level baud rate clock of 16x or 8x txnofifo- 1 set at below trigger level clear at above trigger level stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx data input first byte that reaches the trigger level rx data ready interrupt at receive trigger level rxfifo1 de-asserted at below trigger level asserted at above trigger level
xr xr17c154 rev. 1.3.2 5v pci bus quad uart 59 n ote : note: the control dimension is the millimeter column package dimensions inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.858 0.874 21.80 22.20 d1 0.783 0.791 19.90 20.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 a 2 l c e 108 73 72 37 109 144 d d 1 d d 1 1 36 b a 1 a seating plane 144 lead low-profile quad flat pack (20 x 20 x 1.4 mm lqfp)
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 60 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet august 2005. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history d ate r evision d escription february 2001 a1.0.1 initial advanced datasheet february 2001 a1.0.2 corrections for the 154 part name and reference to 4 uarts april 2001 p1.0.0 preliminary release sept 2001 1.0.0 further clarified pins functions and text, revised dc characteristics table and added 3.3v dc operating parameters. may 2003 1.1.0 changed to single column format. added uarttechsupport e-mail address to last page. september 2003 1.2.0 added device status to ordering information. clarified rs485 description. added description for pci burst read and pci burst write. added wake-up indicator to inter - rupt source table. june 2004 1.3.0 clarified pin descriptions- changed from using logic 1 and logic 0 to high (vcc) and low (gnd) for input and output pin descri ptions. the xr17c154 is a 5v only pci quad uart (removed 3.3v electrical characte ristics). for a 3.3v pci quad uart, see the xr17d154. the device revision register (drev) has been updated to 0x02 for devices with top mark date code "b2 yyww". november 2004 1.3.1 the device revision register (drev) has been updated to 0x04 for devices with top mark date code "d2 yyww". august 2005 1.3.2 updated the 1.4mm-thick quad flat pack pack age description from "tqfp" to "lqfp" to be consistent with jedec and industry norms.
xr xr17c154 rev. 1.3.2 5v pci bus quad uart i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 a pplications ............................................................................................................................... ................ 1 f eatures ............................................................................................................................... ...................... 1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. p in o ut of the d evice ............................................................................................................................... ................... 2 ordering information ............................................................................................................................... .2 pin descriptions ............ ................ ................ ................. ................ ................. ........... 3 functional description .. ................. ................ ................ ............... .............. ........... 6 pci local bus interface........................................................................................................ ....................................... 6 1.0 xr17c154 registers ...................................................................................................... .................. 7 f igure 3. t he xr17c154 r egister s ets ............................................................................................................................... ..... 7 1.1 pci local bus configuration space registers ............................................................................ 7 t able 1: pci l ocal b us c onfiguration s pace r egisters ......................................................................................................... 8 1.2 device config uration register set ......... .............. .............. .............. .............. ............ .......... ........... 9 t able 2: xr17c154 d evice c onfiguration r egisters ............................................................................................................. 10 t able 3: d evice c onfiguration r egisters shown in byte alignment ................................................................................... 12 t able 4: d evice c onfiguration r egisters shown in dword alignment .............................................................................. 12 1.2.1 the interrupt status register .......................................................................................... ........................... 13 f igure 4. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 .................................................................................. 14 t able 5: uart c hannel [3:0] i nterrupt s ource e ncoding ..................................................................................................... 14 t able 6: uart c hannel [3:0] i nterrupt c learing ................................................................................................................... 14 1.2.2 general purpose 16-bit timer/counter [timer msb, timelsb, timer, timecntl] (default 0xxx-xx- 00-00) ......................................................................................................................... .................................................... 15 f igure 5. t imer /c ounter circuit ............................................................................................................................... ................ 15 t able 7: timer control r egisters ............................................................................................................................... ....... 15 1.2.3 8xmode [7:0] (default 0x00)............................................................................................ .................................... 16 1.2.4 rega [15:8] reserved ................................................................................................... ........................................ 16 1.2.5 reset [23:16] (default 0x00)........................................................................................... .................................... 16 1.2.6 sleep [31:24].......................................................................................................... ....................... (default 0x00) 17 1.2.7 device identification and revision..................................................................................... .......................... 17 1.2.8 regb register .......................................................................................................... ............................................. 18 1.2.9 multi-purpose inputs and outputs ....................................................................................... ....................... 18 1.2.10 mpio register ......................................................................................................... ............................................. 18 f igure 6. m ultipurpose input / output internal circuit ........................................................................................................... 19 2.0 crystal oscillator / buffer ............................................................................................. ...... 21 f igure 7. t ypical oscillator connections ............................................................................................................................... 21 f igure 8. e xternal c lock c onnection for e xtended d ata r ate .......................................................................................... 21 3.0 transmit and receive data ............................................................................................... ....... 22 3.1 data loading and unloading vi a 32-bit pci burst transfers ........ ........... ............ ........... ..... 22 3.1.1 normal rx fifo data unloading at locations 0x100, 0x300, 0x500, 0x700........................................ 22 3.1.2 special rx fifo data unloading at locations 0x180, 0x380, 0x580, and 0x780 .............................. 23 3.1.3 tx fifo data loading at locations 0x100, 0x300, 0x500, 0x700 ............................................................. 23 3.2 fifo data loading and unloading through the u art channel registers, thr and rhr in 8-bit format .................................................................................................................. ............................ 24 t able 8: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible ............................................................ 24 4.0 uart .................................................................................................................... ................................ 25 4.1 programmable baud rate generat or .......... .............. .............. .............. .............. ........... ........... ... 25 f igure 9. b aud r ate g enerator ............................................................................................................................... ................ 25 t able 9: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling .......................................... 26 4.2 transmitter ............................................................................................................. .................................. 26 4.2.1 transmit holding register (thr) - write-only........................................................................... .............. 26 4.2.2 transmitter operation in non-fifo mode ................................................................................. ................. 26 f igure 10. t ransmitter o peration in non -fifo m ode ............................................................................................................ 27 4.2.3 transmitter operation in fifo mode ..................................................................................... ...................... 27 4.2.4 auto rs485 operation ................................................................................................... ..................................... 27 f igure 11. t ransmitter o peration in fifo and f low c ontrol m ode ................................................................................... 27 4.3 receiver ................................................................................................................ ...................................... 28 4.3.1 receive holding register (rhr) - read-only ............................................................................ ............... 28 4.3.2 receiver operation in non-fifo mode ................................................................................... ..................... 28 f igure 12. r eceiver o peration in non -fifo m ode .................................................................................................................. 28
xr17c154 xr 5v pci bus quad uart rev. 1.3.2 ii 4.3.3 receiver operation with fifo ........................................................................................... .............................. 29 f igure 13. r eceiver o peration in fifo and f low c ontrol m ode ......................................................................................... 29 4.4 automatic hardware (rts/cts or dtr/dsr) flow control operation .............................. 29 t able 10: a uto rts/cts or dtr/dsr f low c ontrol s election .......................................................................................... 29 f igure 14. a uto rts/dtr and cts/dsr f low c ontrol o peration ...................................................................................... 30 4.5 infrared mode ........................................................................................................... ............................... 31 f igure 15. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 31 4.6 internal loopback ....................................................................................................... .......................... 32 f igure 16. i nternal l oop b ack ............................................................................................................................... .................. 32 4.7 uart channel configuration re gisters and address decoding . .............. ............... ......... 32 t able 11: uart channel configuration registers ..................................................................................... .............. 33 t able 12: uart channel configurat ion registers description. s haded bits are enabled by efr b it -4. ....... 34 4.8 registers ............................................................................................................... ..................................... 35 4.8.1 receive holding register (rhr) - read-only ............................................................................. ............... 35 4.8.2 transmit holding register (thr) - write-only........................................................................... .............. 35 4.8.3 baud rate generator divisors (dll and dlm) - read/write................................................................ 35 4.8.4 interrupt enable register (ier) - read/write ........................................................................... ............... 35 ier versus receive fifo interrupt mode operation..... .......................................................................... .................. 35 ier versus receive/transmit fifo po lled mode operation ......................................................................... ............ 35 4.8.5 interrupt status register (isr) - read-only............................................................................ ................ 36 t able 13: i nterrupt s ource and p riority l evel ..................................................................................................................... 37 4.8.6 fifo control register (fcr) - write-only ............................................................................... ................... 38 t able 14: t ransmit and r eceive fifo t rigger l evel s election ............................................................................................ 39 4.8.7 line control register (lcr) - read/write ............................................................................... ................... 40 t able 15: p arity selection ............................................................................................................................... ......................... 41 4.8.8 modem control regist er (mcr) - read/write .............................................................................. ............. 41 4.8.9 line status register (lsr) - read/only ................................................................................. ...................... 42 4.8.10 modem status register (msr) - read-only ............................................................................... ............... 43 4.8.11 modem status register (msr) - write-only .............................................................................. ............... 44 t able 16: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive ................................................. 44 4.8.12 scratch pad register (spr) - read/write............................................................................... .................. 45 4.8.13 feature control register (fctr) - read/write ......................................................................... ........... 45 t able 17: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected ................................................................ 46 4.8.14 enhanced feature register (efr) - read/write.......................................................................... ........... 46 t able 18: s oftware f low c ontrol f unctions ........................................................................................................................ 47 4.8.15 txcnt[7:0]: transmit fifo l evel counter - read-only ................................................................... ...... 48 4.8.16 txtrg [7:0]: transmit fifo trigger level - write-only ................................................................. ....... 48 4.8.17 rxcnt[7:0]: receive fifo level counter - read-only .................................................................... ........ 48 4.8.18 rxtrg[7:0]: receive fifo trigger level - write-only................................................................... ......... 48 t able 19: uart reset conditions .................................................................................................... .................................. 49 5.0 programming examples .................................................................................................... .........50 5.1 unloading receive data using the special re ceive fifo data with status ...... ............ 50 absolute maximum ratings........... ................ ................ ............... .............. ...........51 electrical characteristics ........ ................ ................ ............... .............. ...........51 dc electrical characteristics for 5v signaling .................................................................51 ac electrical characteristics for 5v signaling ...................................................................52 f igure 17. pci b us c onfiguration s pace r egisters r ead and w rite operation ................................................................. 53 f igure 18. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword ...................................... 54 f igure 19. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o peration ..................... 55 f igure 20. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration ........................ 56 f igure 21. 5v pci b us c lock (dc to 33mh z ) .......................................................................................................................... 57 f igure 22. t ransmit d ata i nterrupt at t rigger l evel ........................................................................................................... 58 f igure 23. r eceive d ata r eady i nterrupt at t rigger l evel .................................................................................................. 58 package dimensions........ ................. ................ ................ ............... .............. ...........59 r evision h istory .............................................................................................................................. ........60 t able of c ontents ................ ................. ................ ................ ............... .............. .............. i

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